| Dflipflop Project Status | |||
| Project File: | Dflipflop.xise | Parser Errors: | No Errors |
| Module Name: | Dflipflop | Implementation State: | Programming File Generated |
| Target Device: | xc3s400-4pq208 |
|
No Errors |
| Product Version: | ISE 14.7 |
|
No Warnings |
| Design Goal: | Balanced |
|
All Signals Completely Routed |
| Design Strategy: | Xilinx Default (unlocked) |
|
All Constraints Met |
| Environment: | System Settings |
|
0 (Timing Report) |
| Device Utilization Summary | [-] | ||||
| Logic Utilization | Used | Available | Utilization | Note(s) | |
| Number of Slices containing only related logic | 0 | 0 | 0% | ||
| Number of Slices containing unrelated logic | 0 | 0 | 0% | ||
| Number of bonded IOBs | 4 | 141 | 2% | ||
| IOB Flip Flops | 1 | ||||
| Number of BUFGMUXs | 1 | 8 | 12% | ||
| Average Fanout of Non-Clock Nets | 0.50 | ||||
| Performance Summary | [-] | |||
| Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report | |
| Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
| Timing Constraints: | All Constraints Met | |||
| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos | |
| Synthesis Report | Current | Tue Dec 25 20:39:41 2018 | 0 | 0 | 0 | |
| Translation Report | Current | Tue Dec 25 20:39:48 2018 | 0 | 0 | 0 | |
| Map Report | Current | Tue Dec 25 20:39:57 2018 | 0 | 0 | 2 Infos (2 new) | |
| Place and Route Report | Current | Tue Dec 25 20:40:03 2018 | 0 | 0 | 1 Info (1 new) | |
| Power Report | ||||||
| Post-PAR Static Timing Report | Current | Tue Dec 25 20:40:06 2018 | 0 | 0 | 6 Infos (6 new) | |
| Bitgen Report | Current | Tue Dec 25 20:40:10 2018 | 0 | 0 | 1 Info (1 new) | |
| Secondary Reports | [-] | ||
| Report Name | Status | Generated | |
| ISIM Simulator Log | Out of Date | Tue Dec 25 16:03:20 2018 | |
| WebTalk Report | Current | Tue Dec 25 20:40:11 2018 | |
| WebTalk Log File | Current | Tue Dec 25 20:40:17 2018 | |