Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:14.7 (WebPack) - P.20131013 Target Family: Spartan3
OS Platform: NT64 Target Device: xc3s400
Project ID (random number) bd68bcdf783a4412a67969d16024b4b9.6EBC7848A936447780A281259D98667F.1 Target Package: pq208
Registration ID __0_0_0 Target Speed: -4
Date Generated 2018-12-25T20:40:11 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows 7 , 64-bit OS Release Service Pack 1 (build 7601)
CPU Name Intel(R) Pentium(R) CPU G3220 @ 3.00GHz CPU Speed 2993 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Registers=1
  • Flip-Flops=1
 		MiscellaneousStatistics
  • AGG_BONDED_IO=4
  • AGG_IO=4
  • NUM_BONDED_IOB=4
  • NUM_BUFGMUX=1
  • NUM_IOB_FF=1
 		NetStatistics
  • NumNets_Active=8
  • NumNets_Vcc=1
  • NumNodesOfType_Active_CLKPIN=1
  • NumNodesOfType_Active_CNTRLPIN=1
  • NumNodesOfType_Active_DOUBLE=2
  • NumNodesOfType_Active_DUMMY=2
  • NumNodesOfType_Active_DUMMYESC=3
  • NumNodesOfType_Active_GLOBAL=5
  • NumNodesOfType_Active_INPUT=2
  • NumNodesOfType_Active_IOBOUTPUT=3
  • NumNodesOfType_Active_OUTPUT=1
  • NumNodesOfType_Vcc_CNTRLPIN=1
  • NumNodesOfType_Vcc_VCCOUT=1
 SiteStatistics
  • IOB-DIFFM=3
  • IOB-DIFFS=1
 		SiteSummary
  • BUFGMUX=1
  • BUFGMUX_GCLKMUX=1
  • BUFGMUX_GCLK_BUFFER=1
  • IOB=4
  • IOB_INBUF=3
  • IOB_OFF1=1
  • IOB_OUTBUF=1
  • IOB_PAD=4
 
Configuration Data
BUFGMUX
  • S=[S_INV:1] [S:0]
 BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:1]
  • S=[S_INV:1] [S:0]
 IOB
  • O1=[O1_INV:0] [O1:1]
  • OTCLK1=[OTCLK1_INV:0] [OTCLK1:1]
  • SR=[SR:0] [SR_INV:1]
 IOB_OFF1
  • CK=[CK:1] [CK_INV:0]
  • D=[D:1] [D_INV:0]
  • LATCH_OR_FF=[FF:1]
  • OFF1_INIT_ATTR=[INIT0:1]
  • OFF1_SR_ATTR=[SRLOW:1]
  • OFFATTRBOX=[SYNC:1]
  • SR=[SR:0] [SR_INV:1]
 IOB_OUTBUF
  • IN=[IN_INV:0] [IN:1]
 IOB_PAD
  • DRIVEATTRBOX=[12:1]
  • IOATTRBOX=[LVCMOS25:4]
  • SLEW=[SLOW:1]
 
Pin Data
BUFGMUX
  • I0=1
  • O=1
  • S=1
 BUFGMUX_GCLKMUX
  • I0=1
  • OUT=1
  • S=1
 BUFGMUX_GCLK_BUFFER
  • IN=1
  • OUT=1
 IOB
  • I=3
  • O1=1
  • OTCLK1=1
  • PAD=4
  • SR=1
 IOB_INBUF
  • IN=3
  • OUT=3
 IOB_OFF1
  • CK=1
  • D=1
  • Q=1
  • SR=1
 IOB_OUTBUF
  • IN=1
  • OUT=1
 IOB_PAD
  • PAD=4
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc3s400-pq208-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s400-pq208-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • fuse
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
bitgen 1 1 0 0 0 0 0
map 1 1 0 0 0 0 0
ngdbuild 1 1 0 0 0 0 0
par 1 1 0 0 0 0 0
trce 1 1 0 0 0 0 0
xst 2 2 0 0 0 0 0
 
Project Statistics
PROPEXT_xilxSynthMaxFanout_virtex2=100000 PROP_Enable_Message_Filtering=false
PROP_FitterReportFormat=HTML PROP_LastAppliedGoal=Balanced
PROP_LastAppliedStrategy=Xilinx Default (unlocked) PROP_ManualCompileOrderImp=false
PROP_PropSpecInProjFile=Store all values PROP_SelectedInstanceHierarchicalPath=/Dflipflop
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2018-12-25T15:58:53
PROP_intWbtProjectID=6EBC7848A936447780A281259D98667F PROP_intWbtProjectIteration=1
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_lockPinsUcfFile=changed PROP_selectedSimRootSourceNode_behav=work.Dflipflop
PROP_xilxBitgStart_IntDone=true PROP_AutoTop=true
PROP_DevFamily=Spartan3 PROP_DevDevice=xc3s400
PROP_DevFamilyPMName=spartan3 PROP_DevPackage=pq208
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_DevSpeed=-4
PROP_PreferredLanguage=VHDL FILE_UCF=1
FILE_VHDL=1
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FDR=1 NGDBUILD_NUM_IBUF=2 NGDBUILD_NUM_INV=1
NGDBUILD_NUM_OBUF=1
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_FDR=1 NGDBUILD_NUM_IBUF=2 NGDBUILD_NUM_IBUFG=1
NGDBUILD_NUM_INV=1 NGDBUILD_NUM_OBUF=1
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc3s400-4-pq208 -top=<design_top> -opt_mode=Speed -opt_level=1
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -verilog2001=YES
-fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No -fsm_style=LUT
-ram_extract=Yes -ram_style=Auto -rom_extract=Yes -shreg_extract=YES
-rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES -async_to_sync=NO
-mult_style=Auto -iobuf=YES -max_fanout=100000 -bufg=8
-register_duplication=YES -register_balancing=No -optimize_primitives=NO -use_clock_enable=Yes
-use_sync_set=Yes -use_sync_reset=Yes -iob=Auto -equivalent_register_removal=YES
-slice_utilization_ratio_maxmargin=5
 
ISim Statistics
Xilinx HDL Libraries Used=ieee
Fuse Resource Usage=390 ms, 28156 KB
Total Signals=4
Total Nets=4
Total Blocks=2
Total Processes=1
Total Simulation Time=2 us
Simulation Resource Usage=0.499204 sec, 974360 KB
Simulation Mode=gui
Hardware CoSim=0